Cell-level and pin-level attributes from Liberty are mandatorily required for accurate PA-Static verification at the GL-netlist (post-synthesis) and PG-netlist (post P&R) levels of the design.

AAI (Avnet ASIC Israel Ltd.) recently designed and implemented a group of SoC devices that connect several IPs from different vendors with customer specific IPs, around an industry standard AHB bus.

But even today, some designs don't require top-down methodology or bottom-up verification. Examples include simple analog designs or designs with no feedback between the analog and digital sections.