EDN

Monterey adds Synplicity synthesis to ASIC design flow

SAN MATEO, Calif. — Claiming to have a full RTL-to-GDSII design flow at last, Monterey Design Systems has added logic synthesis to its Dolphin placement and routing system. The Dolphin-RTL synthesis ...
Electronic Design

FPGA Prototyping Tool Aligns With ASIC Flow

This FPGA-Synthesis Tool Offers The Prototyping Capabilities Required By RF-Intensive Systems And A Migration Path To ASIC Product Design. Over a third of all high-end ASIC designers now use FPGAs for ...
Design-Reuse

Faraday Adopts Incentia for ASIC Synthesis & Timing Flow

Runtime speed and capacity of Incentia’s logic, test and low power synthesis & timing software crucial for high-performance, complex design success HSINCHU, Taiwan, and SANTA CLARA, Calif. – June ...
Design-Reuse

Forte Design Systems' SystemC High-Level Synthesis Selected for Fujitsu Semiconductor's ASIC Reference Flow

SAN JOSE, CALIF. –– December 8, 2010 –– Forte Design Systems announced today that Cynthesizer™ high-level synthesis software has been selected for use in Fujitsu Semiconductor Limited’s ...
mccormick.northwestern.edu

COMP_ENG 459: VLSI Algorithmics

Introduction to advanced topics in synthesis and modeling of complex VLSI systems at behavioral and logic level. Topics include resource allocation, resource binding, scheduling, and controller design ...
Semiconductor Engineering

C-Based SoC Design Flow And EDA Tools

This paper examines the achievements and future of SoC design methodology and design flow from the viewpoints of an in- house EDA team of an ASIC and system vendor. We initially discuss the problems ...
TechRepublic

Mapping of Multiple Data Flow Graphs of DSP Applications onto ASIC/Reconfigurable Architectures

In this paper, the authors present a novel technique for the mapping of set of DSP applications onto architectures targeting an ASIC/Reconfigurable implementation embedded on the same chip. Synthesis ...