EDN

Design holds the key to cost-effective SOC testing

The most effective way to shorten test times is to test more of the SOC IP (intellectual-property) cores in parallel. However, for best results, the SOC design should anticipate parallel testing, and ...
Electronic Design

Simplify SoC Development With Embedded Testing

While the use of complex system-on-a-chip (SoC) designs has increased, unfortunately, that hasn't increased the time-to-market window for designers and chip manufacturers. As SoC designs become more ...
Digi Times

Advantest introduces newest parametric measurement module to extend SoC testing capabilities of T2000 platform

Leading semiconductor test equipment supplier Advantest Corporation (TSE: 6857, NYSE: ATE) has launched a new multi-purpose parametric measurement unit (PMU) module, the T2000 PMU32E, to enhance its ...
EDN

Mixed-signal instrument provides multi-site testing of SiP/SoC devices

Milpitas, Calif. — Credence Systems has enhanced its Diamond test platform with the introduction of its MultiWave instrument, a mixed-signal solution for multi-site testing of highly integrated system ...
Electronic Design

DFT Propels SoC IC Testing

The Design-for-Test (DFT) methodology is a strong driving force in the cost-effective testing of large-volume commodity items with very short life cycles, like system-on-chip (SoC) devices. It will ...