EDN

Signal Chain Basics #89: Creating Clock Trees From Multiple Devices, Part 2

This two-part Signal Chain Basics post is brought to you by Dean Banerjee, an applications engineer for TI's Signal and Data Path Solutions Business Unit. Part one can be found here. A good way to ...
Electronic Design

Timing Decisions 102: Optimize Your Clock Tree

The importance of timing requirements and jitter budgets for FPGAs, ASICs, and SoCs. How to utilize the information portrayed in a clock tree to choose the most well-suited clock generator for your ...