EDN

Improving analog design verification using UVM

As technology becomes more integrated into our everyday life, our chips need to better communicate with the analog world. Most modern system on chip (SoC) designs therefore contain analog and ...
Business Wire

MathWorks Speeds FPGA and ASIC Verification with Universal Verification Methodology (UVM) Support

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.
Semiconductor Engineering

Post Layout Simulation Is Becoming The Bottleneck For Analog Verification

My, have times changed. I remember when I first started out as a green analog designer right out of college, we would cut rubylith masking film on a large light table representing the different layers ...
Electronic Design

Dirt Cheap ASIC Design for Dummies (Part 3): NMOS, PMOS Silicon Design Using a Web Browser

Quickly learn what the difference is between PMOS and NMOS transistors in their structure and operation, and how CMOS works with the two in combination. Siliwiz, a free, browser-based, ASIC layout ...
Semiconductor Engineering

Asynchronously Parallel Optimization Method For Sizing Analog Transistors Using Deep Neural Network Learning

A new technical paper titled “APOSTLE: Asynchronously Parallel Optimization for Sizing Analog Transistors Using DNN Learning” was published by researchers at UT Austin and Analog Devices. “Analog ...