Electronic Design

Optimize Timing Margins For Your High-Speed Interface

High-speed digital buses have evolved dramatically over the past decade. Not only are they faster, but they're also changing how systems clock data. To improve data throughput, emerging synchronous ...
EDN

Automating static timing analysis process

EMA Design Automation announced TimingDesigner 9.25 with enhanced Automerge functionality, which the company claims, dramatically decreases the time required for performing interface timing analysis.
EDN

New Cypress 4-PLL Timing Chip Is First With 2-Wire I2C Interface, Allowing On-Board Programming For Fast Time-to-Market And Reduced Inventory

New Cypress 4-PLL Timing Chip Is First With 2-Wire I2C Interface, Allowing On-Board Programming For Fast Time-to-Market And Reduced Inventory Cypress Semiconductor Corp. introduced the industry's ...
Semiconductor Engineering

Timing Signoff Methodology For eFPGA

An eFPGA is a hard IP block in an SoC. Most SoCs are made up of a collection of hard IP blocks (RAM, SerDes, PHYs…) and the remaining logic is constructed using Standard Cells. The timing signoff for ...