Design-Reuse

Mapping LMS Adaptive Filter IP Core to Multiplier-Array FPGA Architecture for High Channel-Density VOIP Line Echo Cancellation

The LMS adaptive filter is the main functional block in high channel-density line echo cancellers for VOIP. In this paper, we describe an LMS adaptive FIR filter IP and estimate its performance when ...
Electronic Design

16-nm FPGA Includes 64-bit and Lockstep ARM Cortex Cores

Xilinx's latest FPGAs move down to 16-nm. This includes the latest Virtex UltraSCALE+ and Kintex UltraSCALE+. The Zynq line (see “FPGA Packs In Dual Cortex-A9 Micro”) gains a big brother with the Zynq ...
EDN

16-bit pipelined serial/parallel multiplier using Mentor Graphics Tools

Designed the 16-bit pipelined serial/parallel multiplier by utilizing the MOSIS (TSMC) 0.35 μm CMOS process. The 16-bit Pipelined Serial/Parallel Multiplier is capable of multiplying two 16-bit ...
Electronic Design

Embedded FPGA Under the Hood

For the most part, embedded FPGA can be viewed as a “black box,” which is effectively as an RTL engine. However, sometimes it’s helpful to understand what’s going on underneath the hood to evaluate ...