EDN

Pre-configured DFT structures can simplify ASIC design, verification

Steven Kawamoto, Sr. Marketing Manager, Custom LSI Solutions Unit, Gaku Ogura, Sr. Marketing Manager, Design Solutions Center, Richard Lee, Design Engineer, Design ...
EDN

Architecture-based vs. flow-based approach to DFT

Increases in the average gate count of ASIC designs is forcing design teams to spend 20 percent to 50 percent of their ASIC development effort on test-related concerns to achieve good test coverage.
Design-Reuse

Faraday Adopts Incentia for ASIC Synthesis & Timing Flow

Runtime speed and capacity of Incentia’s logic, test and low power synthesis & timing software crucial for high-performance, complex design success HSINCHU, Taiwan, and SANTA CLARA, Calif. – June ...
Electronic Design

Mentor targets hierarchical DFT and automotive safety

Hierarchical DFT methodology and automotive functional safety have been two recent areas of focus for Mentor, a Siemens business. Legacy design-for-test flows impose inefficiencies when transitioning ...
Design-Reuse

EnSilica teams with BaySand to provide ASIC UltraShuttle-65 multi-project wafer customers with configurable IP solutions

EnSilica to provide BaySand’s customers with configurable eSi-RISC processor cores, eSi-Connect processor peripherals, eSi-Crypto encryption and eSi-Comms communications IP solutions as well hardware ...